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ADR-001: Lock-Free IPC Architecture

Status​

Accepted

Context​

The VR overlay system requires extremely low-latency communication between processes to maintain the 144Hz frame rate target. Traditional IPC mechanisms with locking primitives introduce unacceptable latency and jitter.

Decision​

We will implement a lock-free IPC system using:

  • Single-writer, multiple-reader ring buffers
  • Atomic operations for coordination
  • Shared memory segments for zero-copy data transfer
  • Wait-free algorithms where possible

Consequences​

Positive​

  • Predictable sub-25μs latency (p95)
  • No priority inversion issues
  • Scales well with multiple readers
  • Enables real-time guarantees

Negative​

  • More complex implementation
  • Requires careful memory ordering
  • Limited to single-writer patterns
  • Debugging is more challenging

Implementation​

See the detailed IPC documentation at IPC System Design.